Technical Program

Friday, May 31, 2019

Session 35: New Interconnects for Package Scaling
1:30 PM - 5:10 PM
Committee: Interconnections

Session Co-Chairs:

David Danovitch
University of Sherbrooke
T +1-450-534-8000 X-1400
David.Danovitch@USherbrooke.ca
Katsuyuki Sakuma
IBM Corporation
T +1-914-945-2080
ksakuma@us.ibm.com

Papers:

1. 1:30 PM - Development of 2.3D High Density Organic Package Using Low Temperature Bonding Process With Sn-Bi Solder
Shota Miki - Shinko Electric Industries Co. Ltd.
Hiroshi Taneda - Shinko Electric Industries Co. Ltd.
Naoki Kobayashi - Shinko Electric Industries Co. Ltd.
Kiyoshi Oi - Shinko Electric Industries Co. Ltd.
Koji Nagai - Shinko Electric Industries Co. Ltd.
Toshinori Koyama - Shinko Electric Industries Co. Ltd.

2. 1:55 PM - PowerTherm Attachment Process for Power Delivery and Heat Extraction in the Silicon-Interconnect Fabric
Pranav Ambhore - University of California, Los Angeles
Boris Vaisband - University of California, Los Angeles
Umesha Mogera - University of California, Los Angeles
Ujash Shah - University of California, Los Angeles
Timothy Fisher - University of California, Los Angeles
Mark Goorsky - University of California, Los Angeles
Subramaniam Iyer - University of California, Los Angeles

3. 2:20 PM - Interconnect Scheme for Die-to-Die and Die-to-Wafer Level Heterogeneous Integration for High-Performance Computing
Rabindra Das - Massachusetts Institute of Technology
Vladimir Bolkhovsky - Massachusetts Institute of Technology
Christopher Galbraith - Massachusetts Institute of Technology
Daniel Oates - Massachusetts Institute of Technology
Scott Zarr - Massachusetts Institute of Technology
Jason Plant - Massachusetts Institute of Technology
Terence Weir - Massachusetts Institute of Technology
Leonard Johnson - Massachusetts Institute of Technology
Eric Dauler - Massachusetts Institute of Technology

4. 3:30 PM - Ultra-Wide Micro Bumps Interconnection Matrix for High-Energy Particle Detection: Process and Assembly
Jean Charbonnier - CEA-LETI
Myriam Assous - CEA-LETI
Thierry Mourier - CEA-LETI
Celine Ribière - CEA-LETI
Pierre Tissier - CEA-LETI
Remi Coquand - CEA-LETI
Mehmet Bicer - CEA-LETI
Gabriel Pares - CEA-LETI

5. 3:55 PM - Growth Behavior and orientation Evolution of Cu6Sn5 Grains During the Formation of Full IMC Micro Interconnects
Ning Zhao - Dalian University of Technology
Shi Chen - Dalian University of Technology
C.M.L. Wu - City University of Hong Kong
Yunpeng Wang - Dalian University of Technology
Haitao Ma - Dalian University of Technology

6. 4:20 PM - Development of a No Reflow Cu Pillar Bump to Improve Chip/Package Interactions (CPI) Process and Reliability Performance
Jiunn Jie Wang - Siliconware Precision Industries Co., Ltd.
Yen Neng Wang - Siliconware Precision Industries Co., Ltd.
Feng Lung Chien - Siliconware Precision Industries Co., Ltd.
Rick Lee - Siliconware Precision Industries Co., Ltd.

7. 4:45 PM - A Novel Interconnection Technology Using Ultra-Thin Under Barrier Metal for Multiple Chip-on-Chip Stacking Structure
Satoru Wakiyama - Sony Semiconductor Solutions Corporation
Takuya Nakamura - Sony Semiconductor Solutions Corporation
Kan Shimizu - Sony Semiconductor Solutions Corporation
Masataka Maehara - Sony Semiconductor Solutions Corporation
Toshihiko Hayashi - Sony Semiconductor Solutions Corporation
Kentaro Akiyama - Sony Semiconductor Solutions Corporation
Junichiro Fujimagari - Sony Semiconductor Solutions Corporation
Tomohiro Ohkubo - Sony Semiconductor Solutions Corporation
Atsushi Fujiwara - Sony Semiconductor Solutions Corporation
Hayato Iwamoto - Sony Semiconductor Solutions Corporation