Technical Program

Friday, June 01, 2018

Session 35: New Interconnects for Package Scaling
1:30 PM - 5:10 PM
Committee: Interconnections

Session Co-Chairs:

David Danovitch
University of Sherbrooke
T +1-450-534-8000 X-1400
David.Danovitch@USherbrooke.ca
Katsuyuki Sakuma
IBM Corporation
T +1-914-945-2080
ksakuma@us.ibm.com

Papers:

1. 1:30 PM - Development of 2.3D High Density Organic Package using Low Temperature Bonding Process with Sn-Bi Solder
Shota Miki - Shinko Electric Industries Company, Limited
Hiroshi Taneda - Shinko Electric Industries Company, Limited
Naoki Kobayashi - Shinko Electric Industries Company, Limited
Kiyoshi Oi - Shinko Electric Industries Company, Limited
Koji Nagai - Shinko Electric Industries Company, Limited
Toshinori Koyama - Shinko Electric Industries Company, Limited

2. 1:55 PM - PowerTherm Attachment Process for Power Delivery and Heat Extraction in the Silicon-Interconnect Fabric
Pranav Ambhore - University of California Los Angeles
Boris Vaisband - University of California Los Angeles
Umesha Mogera - University of California Los Angeles
Ujash Shah - University of California Los Angeles
Timothy Fisher - University of California Los Angeles
Mark Goorsky - University of California Los Angeles
Subramaniam Iyer - University of California Los Angeles

3. 2:20 PM - Interconnect Scheme for Die-to-Die and Die-to-Wafer Level Heterogeneous Integration for High-Performance Computing
Rabindra Das - MIT Lincoln Laboratory
Vladimir Bolkhovsky - MIT Lincoln Laboratory
Christopher Galbraith - MIT Lincoln Laboratory
Daniel Oates - MIT Lincoln Laboratory
Scott Zarr - MIT Lincoln Laboratory
Jason Plant - MIT Lincoln Laboratory
Terence Weir - MIT Lincoln Laboratory
Leonard Johnson - MIT Lincoln Laboratory
Eric Dauler - MIT Lincoln Laboratory

4. 3:30 PM - Ultra Wide Micro bumps interconnection matrix for high energy particle detection: process and assembly.
Jean Charbonnier - CEA-LETI
Myriam Assous - CEA-LETI
Thierry Mourier - CEA-LETI
Celine Ribière - CEA-LETI
Pierre Tissier - CEA-LETI
Remi Coquand - CEA-LETI
Mehmet Bicer - CEA-LETI
Gabriel Pares - CEA-LETI

5. 3:55 PM - Growth behavior and orientation evolution of Cu6Sn5 grains during the formation of full IMC micro interconnects
Ning Zhao - Dalian University of Technology
Shi Chen - Dalian University of Technology
C.M.L. Wu - City University of Hong Kong
Yunpeng Wang - Dalian University of Technology
Haitao Ma - Dalian University of Technology

6. 4:20 PM - Development of a no reflow Cu pillar bump to improve chip/package interactions (CPI) process and reliability performance
Jiunn Jie Wang - SPIL
Yen Neng Wang - SPIL
Feng Lung Chien - SPIL
Rick Lee - SPIL

7. 4:45 PM - A novel interconnection technology using ultra-thin under barrier metal for multiple chip-on-chip stacking structure
Satoru Wakiyama - Sony Semiconductor Solutions
Takuya Nakamura - Sony Semiconductor Solutions
Kan Shimizu - Sony Semiconductor Solutions
Masataka Maehara - Sony Semiconductor Solutions
Toshihiko Hayashi - Sony Semiconductor Solutions
Kentaro Akiyama - Sony Semiconductor Solutions
Junichiro Fujimagari - Sony Semiconductor Solutions
Tomohiro Ohkubo - Sony Semiconductor Manufacturing
Atsushi Fujiwara - Sony Semiconductor Manufacturing
Hayato Iwamoto - Sony Semiconductor Solutions