Technical Program

Program Sessions: Friday June 2nd 9:30 AM – 12:35 PM

Session 25: Next Generation High-Performance Computing Architectures
Committee: Packaging Technologies
Room: Palazzo D

Session Co-Chairs:

Eric Tremble
Marvell
Email: [email protected]

Subhash L. Shinde
Notre Dame University
Email: [email protected]

Papers:

1. CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package
Yu-Min Liang – Taiwan Semiconductor Manufacturing Company, Ltd.
Hsieh-Pin Hu – Taiwan Semiconductor Manufacturing Company, Ltd.
Yu-Chen Hu – Taiwan Semiconductor Manufacturing Company, Ltd.
Chia-Yen Tan – Taiwan Semiconductor Manufacturing Company, Ltd.
Chih-Ta Shen – Taiwan Semiconductor Manufacturing Company, Ltd.
S. Y. Hou – Taiwan Semiconductor Manufacturing Company, Ltd.

2. Reliability Performance of S-Connect Module (Bridge Technology) for Heterogeneous Integration Packaging
HeeJun Jang – Amkor Technology, Inc.
Kyun Ahn – Amkor Technology, Inc.
Gamhan Yong – Amkor Technology, Inc.
WonHo Choi – Amkor Technology, Inc.
JiHyun Kim – Amkor Technology, Inc.
Dave Hiner – Amkor Technology, Inc.
TaeKyeong Hwang – Amkor Technology, Inc.
Mike Kelly – Amkor Technology, Inc.
WonChul Do – Amkor Technology, Inc.
JinYoung Khim – Amkor Technology, Inc.

3. Advanced Packaging Design Platform for Chiplets and Heterogeneous Integration
Lihong Cao – Advanced Semiconductor Engineering, Inc.
Chen-Chao Wang – ASE Corporate R&D Center
Chih-Yi Huang – ASE Corporate R&D Center

4. FO-EB-T Package Solution for High Performance Computing
Po Yuan (James) Su – Siliconware Precision Industries Co., Ltd.
David Ho – Siliconware Precision Industries Co., Ltd.
Jacy Pu – Siliconware Precision Industries Co., Ltd.
Yu Po Wang – Siliconware Precision Industries Co., Ltd.

5. Die to Wafer Hybrid Cu Bonding for Fine Pitch 3D-IC Applications
Yeongseon Kim – Samsung Electronics Co., Ltd.
Juhyeon Kim – Samsung Electronics Co., Ltd.
Hyoeun Kim – Samsung Electronics Co., Ltd.
Dohyun Kim – Samsung Electronics Co., Ltd.
Seonkyung Seo – Samsung Electronics Co., Ltd.
Chajea Jo – Samsung Electronics Co., Ltd.
Dae-Woo Kim – Samsung Electronics Co., Ltd.

6. Silicon Interposer Based 2.5 D Integration of TeraPHY Chiplet for Co-Packaged Optics
Haiwei Lu – Ayar Labs, Inc.
Chong Zhang – Ayar Labs, Inc.
Chen sun – Ayar Labs, Inc.
Steve Groothuis – Ayar Labs, Inc.
Mark Wade – Ayar Labs, Inc.
Chen Li – Ayar Labs, Inc.
Chandru Ramamurthy – Ayar Labs, Inc.
Norman Chan – Ayar Labs, Inc.
Jie Ding – Ayar Labs, Inc.
Byungchae Kim – Ayar Labs, Inc.
Michael Rust – Ayar Labs, Inc.
Forrest Sedgwick – Ayar Labs, Inc.

7. Direct Bonded Heterogeneous Integration (DBHi): Surface Bridge Approach for Die Tiling
Claudia Cristina Barrera Pulido – IBM Canada, Ltd.
Divya Taneja – IBM Canada, Ltd.
Philip McInnes – IBM Canada, Ltd.
Isabel De Sousa – IBM Canada, Ltd.
Sayuri Kohara – IBM Japan, Ltd.
Akihiro Horibe – IBM Japan, Ltd.
Aakrati Jain – IBM Corporation
Thomas Wassick – IBM Corporation