Session 25 – ECTC

Technical Program

Program Sessions: Friday May 31st 9:30 AM – 12:35 PM

Session 25: High-Performance Computing, Design Challenges, and Solutions
Committee: Packaging Technologies
Room:

Session Co-Chairs:

Eric Tremble
Marvell
Email: [email protected]

Young-Gon Kim
Renesas Electronics America
Email: [email protected]

Papers:

1. An Energy-Efficient Si-Integrated Micro-Cooler for High Power and Power-Density Computing Applications
Yu-Jen Lien — Taiwan Semiconductor Manufacturing Company, Ltd.
Cheng-Chieh Hsieh — Taiwan Semiconductor Manufacturing Company, Ltd.
Terry Ku — Taiwan Semiconductor Manufacturing Company, Ltd.
Li Wang — Taiwan Semiconductor Manufacturing Company, Ltd.
Po-Ju Chen — Taiwan Semiconductor Manufacturing Company, Ltd.
Kcyee Yee — Taiwan Semiconductor Manufacturing Company, Ltd.
C. H. Douglas Yu — Taiwan Semiconductor Manufacturing Company, Ltd.

2. High Power Thermal Test Vehicle With 2-Phase Cooling for AI Datacenters, 5G RAN, and EDGE Compute Nodes
Yang Liu — Nokia Bell Labs
Nagesh Basavanhally — Nokia Bell Labs
Mark Earnshaw — Nokia Bell Labs
Todd Salamon — Nokia Bell Labs
Rick Papazian — Nokia Bell Labs
Ting-Chen Hu — Nokia Bell Labs
Mark Cappuzzo — Nokia Bell Labs
Rose Kopf — Nokia Bell Labs
David Apigo — Nokia Bell Labs
Bob Farah — Nokia Bell Labs

3. Block Level and Package Level Thermal Assessment for Back Side Power Delivery Network
Melina Lofrano — imec
Herman Oprins — imec
Vladimir Cherman — imec
Liesbeth Witters — imec
Anne Jourdain — imec
Geert Van der Plas — imec
Eric Beyne — imec

4. Coax MIL 2.0 – Next Generation Coaxial Magnetic Package Core Inductors for Higher Efficiency Integrated Voltage Regulators
Beomseok Choi — Intel Corporation
Jaeil Baek — Intel Corporation
Brandon Marin — Intel Corporation
Shuren Qu — Intel Corporation
Siddharth Kulasekaran — Intel Corporation
Jose Chavarria — Intel Corporation
Leigh Wojewoda — Intel Corporation
Kaladhar Radhakrishnan — Intel Corporation

5. Integrated Design Ecosystem for Chiplets Heterogeneous Integration and Chip-to-Chip Interconnects in Advanced Packaging Technology
Lihong Cao — Advanced Semiconductor Engineering, Inc. (US)
Chen-Chao Wang — ASE Corporate R&D Center
Chih-Yi Huang — ASE Corporate R&D Center
Hung-Chun Kuo — ASE Corporate R&D Center

6. Thermal and Mechanical Simulations of 3D Packages With Custom High Bandwidth Memory (HBM)
Kamalika Chatterjee — Samsung Semiconductor, Inc.
Yan Li — Samsung Semiconductor, Inc.
Pouya Asrar — Samsung Semiconductor, Inc.
WooPoung Kim — Samsung Semiconductor, Inc.

7. A Novel DC-DC Converter Module Using the Integrated Package Solution (iPaS) Substrate for Next Generation High Performance Computing (HPC) Applications
Shuhei Yamada — Murata Manufacturing Co., Ltd.
Nobuyoshi Adachi — Murata Manufacturing Co., Ltd.
Kazuki Itoyama — Murata Manufacturing Co., Ltd.
Keito Yonemori — Murata Electronics North America, Inc.
Tatsuya Kitamura — Murata Manufacturing Co., Ltd.
Koshi Himeda — Murata Manufacturing Co., Ltd.
Atsushi Yamamoto — Murata Manufacturing Co., Ltd.