Technical Program
Program Sessions: Thursday June 1st 2:00 PM – 5:05 PM
Session 22: Large Substrate Process Integration Challenges
Committee: Assembly and Manufacturing Technology
Room: Mediterranean 1
Session Co-Chairs:
Valerie Oberson
IBM Canada, Ltd.
Email: [email protected]
Jobert Van Eisden
Atotech USA, Inc.
Email: [email protected]
Papers:
1. Extremely Large 3.5D Heterogeneous Integration for the Next-Generation Packaging Technology
Ilbok Lee – Samsung Electronics Co., Ltd.
Soohyun Nam – Samsung Electronics Co., Ltd.
Sungeun Kim – Samsung Electronics Co., Ltd.
Sangho Shin – Samsung Electronics Co., Ltd.
Younglyong Kim – Samsung Electronics Co., Ltd.
Sunkyung Seo – Samsung Electronics Co., Ltd.
Hae Jung Yu – Samsung Electronics Co., Ltd.
Dae-Woo Kim – Samsung Electronics Co., Ltd.
2. Study of Fabrication and Reliability for the Extremely Large 2.5D Advanced Package
Kosuke Murai – Resonac Corporation
Hitoshi Onozeki – Resonac Corporation
Dongchul Kang – Resonac Corporation
Kazue Hirano – Resonac Corporation
Mitsukura Kazuyuki – Resonac Corporation
3. Controlling Underfill on Die in Multi-Chip Heterogeneous Integration With Die Height Delta
Ziyin Lin – Intel Corporation
Wei Li – Intel Corporation
Edvin Cetegen – Intel Corporation
Yang Guo – Intel Corporation
Nai-yuan Liu – Intel Corporation
Ifeanyi Okafor – Intel Corporation
Vipul Mehta – Intel Corporation
Xavier Brun – Intel Corporation
Shan Zhong – Intel Corporation
Hsin-yu Li – Intel Corporation
Christopher Rumer – Intel Corporation
4. Lead Frame Versus Mold Via
Rathin Mandal – Institute of Microelectronics A*STAR
Senthil Kumar Munirathinam – PEP Innovation Pte. Ltd.
Jimmy Chew – PEP Innovation Pte. Ltd.
Amlan Sen – PEP Innovation Pte. Ltd.
5. A Novel Low-Temperature Connection and High-Temperature Curing Process for Reducing the Warpage of Bonding Pair in Fan-Out Wafer Level Packaging
Yun Bai – Chinese Academy of Science-Shenzhen Institute of Advanced Technology
Kang Li – Chinese Academy of Science-Shenzhen Institute of Advanced Technology
Cheng Zhong – Chinese Academy of Science-Shenzhen Institute of Advanced Technology
Qiang Liu – Chinese Academy of Science-Shenzhen Institute of Advanced Technology
Jinhui Li – Chinese Academy of Science-Shenzhen Institute of Advanced Technology
Guoping Zhang – Chinese Academy of Science-Shenzhen Institute of Advanced Technology
Rong Sun – Chinese Academy of Science-Shenzhen Institute of Advanced Technology
6. Package Warpage of Whole Strip Evaluation With Interface Analysis in the Flip- Chip Die Bonding Process
Ian Ho – Siliconware Precision Industries Co., Ltd.
Po-Yu Liao – Siliconware Precision Industries Co., Ltd.
Teny Shih – Siliconware Precision Industries Co., Ltd.
Andrew Kang – Siliconware Precision Industries Co., Ltd.
Yu-Po Wang – Siliconware Precision Industries Co., Ltd.
7. Thermal Solutions for High Performance Packages of Large Die and Large Packages
Choong Kooi Chee – Marvell Semiconductor, Inc.
Sean Hsu – Marvell Semiconductor, Inc.
Janak Patel – Marvell Semiconductor, Inc.
Alaba Bamido – Marvell Semiconductor, Inc.
