Session 20 – ECTC

Technical Program

Program Sessions: Thursday May 30th 2:00 PM – 5:05 PM

Session 20: Novel High-Density 3D & Thru-Via Structures and Processes
Committee: Interconnections

Session Co-Chairs:

David Danovitch
University of Sherbrooke
Email: [email protected]

Yoshihsia Kagawa
Email: [email protected]


1. Integration of Planarized Nb-Based Vias to Form a Multi-Level Superconducting Back-End-of-Line
Candice Thomas — Grenoble Alps University/CEA-LETI
Edouard Deschaseaux — Grenoble Alps University/CEA-LETI
Rémi Vélard — Grenoble Alps University/CEA-LETI
Giovanni Romano — Grenoble Alps University/CEA-LETI
Jean-Philippe Michel — Grenoble Alps University/CEA-LETI
Norman Vivien — Grenoble Alps University/CEA-LETI
Richard Souil — Grenoble Alps University/CEA-LETI
Cassandre Beluffi — Grenoble Alps University/CEA-LETI
Catherine Pellissier — Grenoble Alps University/CEA-LETI
Jean Charbonnier — Grenoble Alps University/CEA-LETI

2. Observation of Thermal Expansion Behavior of Nanotwinned-Cu/SiO2 & Regular-Cu/SiO2 Hybrid Structure Via In-Situ Heating AFM
Huai-En Lin — National Yang Ming Chiao Tung University
Chih Chen — National Yang Ming Chiao Tung University
Wei-Lan Chiu — Industrial Technology Research Institute
Hsiang-Hung Chang — Industrial Technology Research Institute

3. 3D Interconnects for Quantum Computing
Jaber Derakhshandeh — imec

4. Laser Drilling of Around 3-Micron Via Into Ajinomoto Build-Up Film
Toshio Otsu — University of Tokyo
Shuntaro Tani — University of Tokyo
Shoko Nagayama — Ajinomoto Fine-Techno Co., Inc.
Ryo Miyamoto — Ajinomoto Fine-Techno Co., Inc.
George Okada — Spectronix Corp., Ltd.
Naoyuki Nakamura — Mitsubishi Electric Corporation
Junichi Nishimae — Mitsubishi Electric Corporation
Hiroharu Tamaru — University of Tokyo
Yohei Kobayashi — University of Tokyo

5. Thermo-Mechanical Reliability Analysis and Raman Spectroscopy Characterization of Sub-micron Through Silicon Vias (TSVs) for Backside Power Delivery in 3D Interconnects
Shuhang Lyu — Purdue University
Thomas Beechem — Purdue University
Tiwei Wei — Purdue University

6. Organic Interposers Using Zero-Misalignment-Via Technology and Silicon Wafer Carriers for Large Area Wafer-Level Package Applications
Alekdandar Aleksov — Intel Corporation
Tushar Talukdar — Intel Corporation
Veronica Strong — Intel Corporation
Holly Sawyer — Intel Corporation
Carolyn Aubertine — Intel Corporation
Johanna Swan — Intel Corporation
Thomas Sounart — Intel Corporation

7. Bendability Enhancement and Miniaturization of Through-X Via (TXV) Based on Flexible Fan-Out Wafer-Level Packaging With Additive Tiny Cu Pillar Assembly
Atsushi Shinoda — Tohoku University
Chang Liu — Tohoku University
Akihiro Tominaga — Tohoku University
Hisashi Kino — Tohoku University
Tetsu Tanaka — Tohoku University
Takafumi Fukushima — Tohoku University