Technical Program

Program Sessions: Thursday June 1st 9:30 AM – 12:35 PM

Session 13: Wafer/Panel-Level and Advanced Substrate Technologies
Committee: Packaging Technologies
Room: Palazzo D

Session Co-Chairs:

Markus Leitgeb
Email: [email protected]

Dean Malta
Micross Advanced Interconnect Technology
Email: [email protected]


1. Supercarrier Redistribution Layer to Realize Ultra High Performance 2.5D Wafer Scale Packaging by CoWoS
S.Y. Hou – Taiwan Semiconductor Manufacturing Company, Ltd.
Chien Hsun Lee – Taiwan Semiconductor Manufacturing Company, Ltd.
Tsung Ding Wang – Taiwan Semiconductor Manufacturing Company, Ltd.
Hao Cheng Hou – Taiwan Semiconductor Manufacturing Company, Ltd.

2. Development of Fine Pitch Backside Redistribution Layer (BRDL) Process in Fan-Out Panel Level Packaging (FOPLP)
Hyunju Lee – Samsung Electronics Co., Ltd.
Sung Keun Park – Samsung Electronics Co., Ltd.
Jaemok Jung – Samsung Electronics Co., Ltd.
Kwangok Jung – Samsung Electronics Co., Ltd.
Ju-il Choi – Samsung Electronics Co., Ltd.
Un-Byoung Kang – Samsung Electronics Co., Ltd.
Dongwoo Kang – Samsung Electronics Co., Ltd.

3. Fabrication of Two-types Full Panel-Sized Interposers With Fine Cu Wirings and Outstanding Electrical Reliability
Masaya Toba – Resonac Corporation
Masashi Minami – Resonac Corporation
Daisuke Yamanaka – Resonac Corporation
Kazuyuki Mitsukura – Resonac Corporation

4. Warpage Modulation for Panel-Level Compression Molding Technology for Heterogeneous Integration Packaging Architectures
Liang He – Intel Corporation
Jason Xie – Intel Corporation
Shishir Deshpande – Intel Corporation
Andrew Jimenez – Intel Corporation
Jung Kyu Han – Intel Corporation
Gang Duan – Intel Corporation
Rahul Manepalli – Intel Corporation

5. ASE Fan-Out Panel Level Package Die-Shift Solutions
Ping Ching Shen – Advanced Semiconductor Engineering, Inc.
Sheng Feng Huang – Advanced Semiconductor Engineering, Inc.
Ping Feng Yang – Advanced Semiconductor Engineering, Inc.
Jen Kuang Fang – Advanced Semiconductor Engineering, Inc.

6. Thermal and Mechanical Characterization of Fan-Out Panel Level Packages by Use of Embedded Packaging Test Chips
Gerald Weis – AT&S AG
Vladimir Cherman – imec
Timo Schwarz – AT&S AG
Geert Van der Plas – imec
Johannes Stahr – AT&S AG
Andreas Zluc – AT&S AG

7. Reliability of Heterogeneous Integration on Hybrid Substrate With Ajinomoto Build-Up Film™
Channing Yang – Unimicron Technology Corp.
John Lau – Unimicron Technology Corp.
Gary Chen – Unimicron Technology Corp.
Jones Huang – Unimicron Technology Corp.
Ming Li – ASM Pacific Technology, Ltd.
YH Chen – Unimicron Technology Corp.
T. J. Tseng – Unimicron Technology Corp.