2026 IEEE ECTC Press Kit

Chris Burke
Media Relations Director
[email protected]

Paper 6.3, “Fracture Analysis for CoWoS Reliability Improvement” Ming-Chih (Jason) Yew, TSMC

• Paper 6.3 Figure 8
• Paper 6.3 Figure with caption

Paper 7.4 “Demonstration of an Optical Packaged Substrate with Embedded Silicon Photonic Transceiver for High Performance Chiplet Packaging,” Fumi Nakamura et al, AIST 

• Paper 7.4 Figure 1
• Paper 7.4 Figures 4a and 4b
• Paper 7.4 Figures with caption

Paper 11.2 “Scalable Electroplated Cu and Co Metaconductor for Low Loss 112 to 400 Gbps Wired Communication Interconnects,” S. Jeon et al, University of Florid

• Paper 11.2 Figure 7
• Paper 11.2 Figure with caption 

Paper 14.2 “Panel CMP Co planarization of Heterogeneous Interfaces for Damascene Organic Interposers (L/S = 2/2μm),” K. To et al, Resonac

• Paper 14.2 Figures 7a and 7b
• Paper 14.2 Figures 12b and 12c
• Paper 14.2 Figures with caption

Paper 15.2 “Detachable Glass Waveguide Connector for Co Packaged Optics on Silicon Photonics Platform with <1.5dB/Facet Passive Coupling and 280mW Power Handling,” A. Dasgupta et al, GlobalFoundries

• Paper 15.2 Figure 2
• Paper 15.2 Figure 3
• Paper 15.2 Figures with caption

Paper 18.4, “First Demonstration of 450nm Pitch Cu-Cu Hybrid Bonding with 98% Yield Across 20M Interconnects for Ultra-Dense 3D Integration,” Y. Trickett et al, Applied Materials

• Paper 18.4 Figure 13
• Paper 18.4 Figure with caption

Paper 21.7, “Electroplated Indium Micro-Bumps: Toward Scalable Low Temperature Ultra-Fine Pitch Interconnects,” M. L. Calvo-Muñoz et al, CEA-Leti

• Paper 21.7 Figure 17
• Paper 21.7 Figure with caption

Paper 24.5 “Physics-Constrained Multi-Agent Automation for Design-for-Reliability: From Literature to Auditable Knowledge and Experimental Design” J. Liang, Delft University of Technology

• Paper 24.5 Figure 1
• Paper 24.5 Figure with caption

Paper 26.4 “Robust Wafer-to-Wafer Cu Direct Bonding Process for Multi-Stacked CMOS Directly Bonded to Array (CBA) Technology in Future 3D Flash Memory,” M. Tagami et al, KIOXIA

• Paper 26.4 Figure 13
• Paper 26.4 Figure 14
• Paper 26.4 Figures with caption

Paper 28.2 “First Demonstration of Stitching-Free Exposure over an Ultra-Large 18-Reticle Area with High-Resolution 1.5μm Line/Space on Glass Substrates,” Naoya Sohara et al, USHIO

• Paper 28.2 Figure 5
• Paper 28.2 Figure with caption

Paper 29.1 “Game-Changing Nanosolder Technology: Self-Assembling Adhesives for Sub-10µm Ultra-Fine Interconnects,” J.W. Huh et al, Nopion

• Paper 29.1 Figure 5
• Paper 29.1 Figure 12
• Paper 29.1 Figures with caption

Paper 31.2 “Enabling Scalable Die-to-Wafer Hybrid Bonding Through Die Distortion Correction and Grid Measurement,” Alex Hsu et al, ASML

• Paper 31.2 Figure 6
• Paper 31.2 Figure 10
• Paper 31.2 Figure 12
• Paper 31.2 Figures with caption

Paper 35.3, “Automotive Reliability of Micro-Cu Pillar Bumps for 2.5D Chiplet Integration,” K. Ando et al, Renesas

• Paper 35.3 Figure 6
• Paper 35.3 Figure 13
• Paper 35.3 Figures with caption

Paper 37.15 “A Holistic Study of Board Level Reliability of CoWoS-R Advanced Packaging on OCP Accelerator Modules,” T-Y. Wu et al, TSMC

• Paper 37.15 Figure 5
• Paper 37.15 Figures 8 and 9
• Paper 37.15 Figures with caption

Paper 37.17 “Multi-channel and Multi-scale Optical Performance for a Detachable Edge-Coupling Connector with a Glass Coupler and Expanded Beam in CPO,” Z. Zhang et al, Intel

• Paper 37.17 Table 1
• Paper 37.17 Figure 8
• Paper 37.17 Figures with caption