chair: Sandy Klengel, Fraunhofer IMWS, [email protected]
assistant chair: Tae-Kyu Lee, Cisco Systems, Inc., [email protected]
- fault isolation techniques, metrology, material characterization, use-condition, stress methodology
- 2D, 2.5D, 3D, chiplets/heterogenous integration, Si bridge, WLCSP, FOWLP, FOPLP
- co-packaged optics (CPO), LED, memory devices, IOT, autonomous vehicles/automotive, wire bonded packages, sintered modules
- micro-bump, micro-pillar, Cu-pillar, TSV, RDL, stacked-die, hybrid-bond, flip chip interconnects
- harsh environments, power modules, renewable energy systems, data center application, liquid cooling/ immersion cooling, thermal materials (TIM)
- medical electronics, wearable electronics, displays, AI application, computing, networking systems, HPC, mobile systems
chair: Zia Karim, Yield Engineering Systems, [email protected]
assistant chair: Eric(Wenhao) Li, Applied Materials, [email protected]
- Embedded, power, magnetics, embedded die and passives in substrates
- controlling Warpage, thermal dissipation, package stress, AI/HPC/SerDes packages (2.5/3D)
- application of glass, hybrid materials, substrates, interposers for 2.5D/3D
- innovations in conductive fine pitch traces, via manufacturing, AI/HPC SerDes packages
- innovative packaging processes, methodologies, materials, tools enabling panel level packaging (PLP)
- cost-efficiency/yield perspective, high yield organic interposer 2.xD for panel level packaging (PLP)
chair: Srikrishna Sitaraman, Marvell Technology, [email protected]
assistant chair: Xiao Sun, IMEC, [email protected]
- 5G/6G, IoT, cloud computing – data center, autonomous vehicles, AI/machine learning, Quantum computing;
- Antennas, sensors, power transfer, wired/wireless communications, RF to THz;
- Multiphysics/multiscale modeling & characterization of interconnects, modules, components, and systems;
- Chiplet, heterogeneous Integration, chip-to-chip 2.XD, Interconnect Fabric, die-to-die, SiP/MCM/system co-design (chip/pkg/board), UCIe, HBM/HPC, SerDes;
- CPO,CPC, CPX, opto-Electrical (OE) hybrid integration, analog packaging, power electronics modeling/characterization;
- High-speed/frequency (RF, mmWave, THz) signal integrity, power integrity, and EMI/EMC
chair: Chukwudi Okoro, Corning, [email protected]
assistant chair: Masha Gorchichko, Marvell Technology, Inc., [email protected]
- Novel materials, packaging architectures, additive manufacturing, harsh environments
- system technology co-optimization (STCO), smart manufacturing, digital twin
- sensor integration/packaging, flexible electronics, implantable electronics, medical/bio-electronics
- integrated power challenges, power delivery, thermal Solutions, high current – high voltage devices
- metrology and characterization, benchmarking, failure analysis, hardware security
- quantum computing, cryogenic electronics, sustainability, emerging AI technologies
chair: Frank Libsch, IBM Corporation, [email protected]
assistant chair: Karan Bhangaonkar, Google, [email protected]
- Abstracts may be submitted related to any of the nine major program committee topics.
- Interactive presentations of technical papers are highly encouraged at ECTC.
- They allow for significant interaction between the presenter and attendees, which is especially suited for material that benefits from more explanation than is practical in oral presentations.
- Interactive presentation session papers are published and archived in equal merit with the other ECTC conference papers.
chair: Gang Duan, Samsung Electro-Mechanics America, [email protected]
assistant chair: Tiwei Wei, University of California, Los Angeles, [email protected]
- Chiplet heterogeneous integration, hybrid bonding – C2W& W2W, fan-out wafer level packaging, fan-out panel level packaging, through silicon via (TSV) and nano-TSV through glass via (TGV), through mold via (TMV)
- 2.5D/3D, Si/glass/organic interposers, silicon bridges/local Si interconnects, glass core substrate/advanced multi-core build-up substrate, fine-pitch/multi-layer RDLs, System-in-Package (SiP), wafer-level system integration, panel-level system integration
- thermo-compression/laser assisted/transient liquid phase bonding, low temperature solders, flip-chip, micro-bump, Cu pillar, wirebond, Al ribbon bond, warpage mitigation
- emerging technologies, optical interconnects, quantum interconnects, printable/flexible interconnects, interconnects for SiC/GaN and WBG
- materials/chemistries, conductive/non-conductive adhesives, ACF, underfill materials and molding compounds, thermal interface materials and novel cooling techniques, metrologies, characterization techniques, thermal/mechanical/electrical tests and reliability, sustainable interconnects
- chiplet interconnect design and validation, standards – UCIe/BoW/etc., design and characterization for BPDN, integrated IVR and passives
chair: Vidya Jayaram, Chipletz, [email protected]
assistant chair: Dwayne Shirley, Marvell Semiconductor, Inc., [email protected]
- Hybrid bonding, fan-out packaging, silicon/glass interposer, 2.5D/3D integration, chiplet integration process, wafer-to-wafer bonding, through-silicon via (TSV), die-to-wafer stacking
- wafer-level packaging (WLP), panel-level packaging (PLP), redistribution layer (RDL), die-embedding processes, panel-scale lithography, glass carriers, thinning and handling, system-level scaling
- polymer TIMs, solder and liquid-metal TIMs, emerging TIMs, die-attach materials, thermo-mechanical reliability, high-temperature stable materials, hermetic sealing materials, shock-resistant compounds
- low-k/low-loss dielectrics, dielectric deposition processes, dielectric patterning, capillary underfill (CUF), reworkable underfills, molded underfills (MUF), wafer-level molding materials, thermally conductive underfill/molding compounds
- temporary bonding adhesives, temporary bonding carriers, UV-release adhesives, thermal-release adhesives, debonding processes, low-temperature adhesives, conductive adhesives, adhesive residue suppression
- silicon/glass core substrates, substrate-like package (SLP), novel substrate materials, AI-enhanced materials and processes, low-temperature solders, high aspect ratio vias, EMI shielding materials, materials for co-packaged optics (CPO)
chair: Lihong Cao, Advanced Semiconductor Engineering, Inc., [email protected]
assistant chair: Eric Tremble, Marvell Technology, Inc., [email protected]
- Architectures, integration, thermal solutions of 2.XD, 3D heterogeneous packaging including CPO/CPC
- silicon/organic/glass/diamond interposers and related packaging technology including CPO/CPC
- hybrid/other die-to-die bonding, TSV, backside power delivery
- embedded die/bridge/passives, fan-out wafer/panel-level packaging
- automotive, wireless power and power electronics including SiC/GaN/PMIC/SPS
- bio/medical, RF, MEMS, sensors, wireless, flexible/wearable, IoT
chair: Nicolas Boyer, Ciena Corporation, [email protected]
assistant chair: Hideyuki Nasu, Furukawa Electric Co., Ltd., [email protected]
- Co-packaged optics (CPO), inverse design, hybrid bonding, heterogeneous materials, 2.5D/3D, PIC assembly, wafer-scale integration, interconnects
- datacom, telecom, optical computing, high density I/O, data processing, 5G/6G, IoT, AI
- space, radiation hard, low VOC adhesives, high-temperature, vibration and shock resilience, atmospheric, automotive, defense
- quantum technologies, quantum packaging, healthcare, green energy, agriculture, climate monitoring, under water, low-power
- materials, connectors, packaging materials, FAU and detachables, metamaterials, metasurfaces, fiber bundle connections, low SWaP-C
- characterization, equipment, packaging tools, 3D printing, micro-optics, free space optics, microscopy, fiber attach
chair: Rui Chen, Eastern Michigan University, [email protected]
assistant chair: Ruiyang Liu, Tenstorrent Inc., [email protected]
- Thermal and mechanical simulation and characterization: across packaging technologies, package level, board level, system level, measurements & characterization, correlations, sensitivity & statistical analysis
- Reliability modeling and testing: material constitutive relations, fatigue, fracture mechanics, warpage, electromigration, vibration, shock and drop, moisture
- Modeling for harsh environments: thermo-mechanical, thermal management, cryogenic, humidity, chemical
- Chip-package interaction for heterogeneous integration: co-packaged optics, photonics, quantum computing
- Novel modeling techniques: multi-scale physics, model order reduction, AI/ML, digital twins
- Credible simulations for virtual release: co-design approaches, CFD and process simulations, model verification
Executive Committee
77th ECTC general chair: Przemyslaw Gromala; Robert Bosch Kft.; [email protected]
77th ECTC vice general chair: Bora Baloglu; Tata Electronics; [email protected]
Professional Development Courses
chair: Kitty Pearsall, Capstan Technologies, Inc., [email protected]
assistant chair: Jeff Suhling, Auburn University, [email protected]
