Technical Program

Friday, May 31, 2019

Session 33: Fan-Out, Flip Chip, and WLCSP
1:30 PM - 5:10 PM
Committee: Thermal/Mechanical Simulation & Characterization

Session Co-Chairs:

Ning Ye
Western Digital
T +1-408-801-1278
ning.ye@wdc.com
Wei Wang
Qualcomm Technologies, Inc.
T +1-858-651-5933
weiwng@qti.qualcomm.com

Papers:

1. 1:30 PM - Effect of Time-Dependent Bulk Modulus on Reliability Assessment of Automotive Electronic Control Unit
Hyun Seop Lee - University of Maryland
Bongtae Han - University of Maryland

2. 1:55 PM - Failure Life Prediction of Wafer Level Packaging Using DoS With AI Technology
P.H. Chou - National Tsing Hua University
X.Y. Hsiao - National Tsing Hua University
K. N. Chiang - National Tsing Hua University

3. 2:20 PM - Thermal Cycling Simulation and Sensitivity Analysis of Wafer-Level Chip-Scale Package With Integration of Metal-Insulator-Metal Capacitors
Yong Liu - ON Semiconductor
Yi Zhou - Georgia Institute of Technology
Bill Chen - ON Semiconductor
Suresh K. Sitaraman - Georgia Institute of Technology

4. 3:30 PM - A Sequential Finite Volume Method / Finite Element Analysis of a Power Electronic Semiconductor Chip
Mario Gschwandl - Polymer Competence Center Leoben GmbH
Peter Fuchs - Polymer Competence Center Leoben GmbH
Thomas Antretter - University of Leoben
Martin Pfost - Technical University of Dortmund
Tao Qi - AT & S Austria Technologie & Systemtechnik AG
Thomas Krivec - AT & S Austria Technologie & Systemtechnik AG
Angelika Schingale - Continental AG

5. 3:55 PM - Prediction of TIM Coverage for a Large Form Factor Lidded FCBGA Package With Organic Substrate
Chi Zhang - HiSilicon Technologies Co., Ltd. A Huawei Company
Xiao Hu - HiSilicon Technologies Co., Ltd. A Huawei Company
Chuanjun Hu - HiSilicon Technologies Co., Ltd. A Huawei Company
Jiantao Zheng - HiSilicon Technologies Co., Ltd. A Huawei Company

6. 4:20 PM - Wafer-Level Warpage Modelling and Validation for FOWLP Considering Effects of Viscoelastic Material Properties Under Process Loadings
Zhaohui Chen - Institute of Microelectronics A*STAR
Xiaowu Zhang - Institute of Microelectronics A*STAR

7. 4:45 PM - Board Level Drop Impact Modeling and Validation in Ultra-Thin Package
Shu-Shen Yeh - Taiwan Semiconductor Manufacturing Company Ltd.
P. Y. Lin - Taiwan Semiconductor Manufacturing Company Ltd.
M. C. Yew - Taiwan Semiconductor Manufacturing Company Ltd.
W. Y. Lin - Taiwan Semiconductor Manufacturing Company Ltd.
K. C. Lee - Taiwan Semiconductor Manufacturing Company Ltd.
C. C. Yang - Taiwan Semiconductor Manufacturing Company Ltd.
J. H. Wang - Taiwan Semiconductor Manufacturing Company Ltd.
P. C. Lai - Taiwan Semiconductor Manufacturing Company Ltd.
C. K. Hsu - Taiwan Semiconductor Manufacturing Company Ltd.
Shin-Puu Jeng - Taiwan Semiconductor Manufacturing Company Ltd.