Technical Program

Friday, June 02, 2017

Session 26: 3D Integration Processing and Reliability
8:00 AM - 11:40 AM
Committee: Advanced Packaging
Room: Southern Hemisphere II

Session Co-Chairs:

Rozalia Beica
Dow Electronic Materials
T 1-508-787-4691
rgbeica@dow.com
Dean Malta
Micross Advanced Interconnect Technology
T +1-919-248-8405
Dean.Malta@micross.com

Papers:

1. 8:00 AM - Sub-micron Electrical Interconnection Enabled Ultra-High I/O Density Wafer Level SiP Integration
Chung Jung Wu - Taiwan Semiconductor Manufacturing Company, Ltd.
Tung Liang Shao - Taiwan Semiconductor Manufacturing Company, Ltd.
Hsiao Yun Chen - Taiwan Semiconductor Manufacturing Company, Ltd.
Sheng Tsung Hsiao - Taiwan Semiconductor Manufacturing Company, Ltd.
Yi Li Hsiao - Taiwan Semiconductor Manufacturing Company, Ltd.
Chih Hang Tung - Taiwan Semiconductor Manufacturing Company, Ltd.
Chen Hua Yu - Taiwan Semiconductor Manufacturing Company, Ltd.
Wei Heng Lin - Taiwan Semiconductor Manufacturing Company, Ltd.

2. 8:25 AM - Temporary Bonding and De-bonding for Multichip-to-Wafer 3D Integration Process Using Spin-on Glass and Hydrogenated Amorphous Si
Murugesan Mariappan - Tohoku University
Takafumi Fukushima - Tohoku University
Mitsumasa Koyanagi - Tohoku University

3. 8:50 AM - Cu/Adhesive Hybrid Bonding at 180 °C in H-containing HCOOH Vapor Ambient for 2.5D/3D Integration
Ran He - University of Tokyo
Masahisa Fujino - University of Tokyo
Masatake Akaike - University of Tokyo
Taiji Sakai - Fujitsu Semiconductor
Seiki Sakuyama - Fujitsu Semiconductor
Tadatomo Suga - University of Tokyo

4. 10:00 AM - 3D Packaging Challenges for High-End Applications
Rahul Agarwal - GLOBALFOUNDRIES
Sukeshwar Kannan - GLOBALFOUNDRIES
Rick Reed - Amkor Technology, Inc.
Yong Song - Amkor Technology, Inc.
SangHyoun Lee - Amkor Technology, Inc.
WangGu Lee - Amkor Technology, Inc.
JinKun Yoo - Amkor Technology, Inc.
Luke England - GLOBALFOUNDRIES

5. 10:25 AM - A Novel Method for Air-gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)
King-Jien Chui - Institute of Microelectronics, A*STAR
Woon Leng Loh - Institute of Microelectronics, A*STAR
Xiangyu Wang - Institute of Microelectronics, A*STAR
Zhaohui Chen - Institute of Microelectronics, A*STAR
Mingbin Yu - Institute of Microelectronics, A*STAR

6. 10:50 AM - Warpage Study of Large 2.5D IC Chip Module
Chieh-Lung Lai - Siliconware Precision Industries Co., Ltd.
Hung-Yuan Li - Siliconware Precision Industries Co., Ltd.
Sam Peng - Siliconware Precision Industries Co., Ltd.
Terren Lu - Siliconware Precision Industries Co., Ltd.
Stephen Chen - Siliconware Precision Industries Co., Ltd.

7. 11:15 AM - Board Level Reliability Optimization for 3D IC Packages with Extra Large Interposer
Laurene Yip - Xilinx, Inc.
Ganesh Hariharan - Xilinx, Inc.
Raghu Chaware - Xilinx, Inc.
Inderjit Singh - Xilinx, Inc.
Tom Lee - Xilinx, Inc.