Technical Program

Wednesday, May 31, 2017

Session 2: TSV Process, Characterization and Applications
8:00 AM - 11:40 AM
Committee: Interconnections
Room: Southern Hemisphere I

Session Co-Chairs:

Takafumi Fukushima
Tohoku University
T +81-22-795-6978
Voya Markovich
Microelectronic Advanced Hardware Consulting, LLC
T +1-631-544-4625


1. 8:00 AM - A Cost-Effective Via Last TSV Technology Using Molten Solder Filling for Automobile Application
Yuki Ohara - DENSO Corporation
Yuki Inagaki - DENSO Corporation
Masaki Matsui - DENSO Corporation
Kazushi Asami - DENSO Corporation

2. 8:25 AM - Accurate Depth Control of Through-Silicon Vias by Substrate Integrated Etch Stop Layers
Matthias Wietstruck - IHP Microelectronics
Steffen Marschmeyer - IHP Microelectronics
Marco Lisker - IHP Microelectronics
Andreas Krueger - IHP Microelectronics
Dirk Wolansky - IHP Microelectronics
Philipp Kulse - IHP Microelectronics
Alexander Goeritz - IHP Microelectronics
Mesut Inac - Technical University Berlin
Thomas Voss - IHP Microelectronics
Andreas Mai - IHP Microelectronics
Mehmet Kaynak - IHP Microelectronics

3. 8:50 AM - Application of a Metallic Cap Layer to Control Cu TSV Extrusion
Golareh Jalilvand - University of Central Florida
Omar Ahmed - University of Central Florida
Keenan Bosworth - University of Central Florida
Zhenlin Pei - University of Central Florida
Cullen Fitzgerald - University of Central Florida
Tengfei Jiang - University of Central Florida

4. 10:00 AM - Development of TSV Electroplating Process for Via-Last Technology
Gilho Hwang - Institute of Microelectronics, A*STAR
Kalaiselvan Ravanethran - Institute of Microelectronics, A*STAR

5. 10:25 AM - Reliability Evaluation of Copper (Cu) Through-Silicon Via (TSV) Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis (PFA)
Jiawei Marvin Chan - Nanyang Technological University
Xu Cheng - Infineon Technologies
Kheng Chooi Lee - Infineon Technologies
Werner Kanert - Infineon Technologies
Chuan Seng Tan - Nanyang Technological University

6. 10:50 AM - Vertical Delay Modeling of Copper/Carbon Nanotube Composites in a Tapered Through Silicon Via
Madhav Rao - International Institute of Information Technology Bangalore

7. 11:15 AM - Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme
SivaChandra Jangam - University of California, Los Angeles
Saptadeep Pal - University of California, Los Angeles
Adeel Bajwa - University of California, Los Angeles
Sudhakar Pamarti - University of California, Los Angeles
Puneet Gupta - University of California, Los Angeles
Subramanian Iyer - University of California, Los Angeles