Technical Program

Wednesday, May 31, 2017

Session 1: Fan-Out Packaging Process and Integration
8:00 AM - 11:40 AM
Committee: Advanced Packaging
Room: Southern Hemisphere II

Session Co-Chairs:

Beth Keser
Intel Corporation
T
beth.keser@intel.com
Mike Ma
Amkor Technology Taiwan (ATT)
T +886-975-778628
mike.ma@amkor.com

Papers:

1. 8:00 AM - Development of a Multi-Project Fan-Out Wafer Level Packaging Platform
Tanja Braun - Fraunhofer IZM
Stefan Raatz - Fraunhofer IZM
Steve Voges - Technical University Berlin
U. Maass - Fraunhofer IZM
Marius van Dijk - Fraunhofer IZM
H. Walter - Fraunhofer IZM
O. Hölck - Fraunhofer IZM
Karl-Friedrich Becker - Fraunhofer IZM
M. Töpper - Fraunhofer IZM
Rolf Aschenbrenner - Fraunhofer IZM
Markus Wöhrmann - Technical University Berlin

2. 8:25 AM - SLIM™, High Density Wafer Level Fan-Out Package Development with Submicron RDL
Youngrae Kim - Amkor Technology, Inc.
JaeHun Bae - Amkor Technology, Inc.
MinHwa Chang - Amkor Technology, Inc.
AhRa Jo - Amkor Technology, Inc.
Ji Hyun Kim - Amkor Technology, Inc.
SangEun Park - Amkor Technology, Inc.
David Hiner - Amkor Technology, Inc.
Mike Kelly - Amkor Technology, Inc.
WonChul Do - Amkor Technology, Inc.

3. 8:50 AM - Development of Novel High Density System Integration Solutions in FOWLP – Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages
André Cardoso - NANIUM S.A.
Alberto Martins - NANIUM S.A.
Hugo Barros - NANIUM S.A.
Elisabete Fernandes - NANIUM S.A.
Abel Janeiro - NANIUM S.A.
Paulo Cardoso - NANIUM S.A.
Leonor Dias - NANIUM S.A.

4. 10:00 AM - Fan-Out Chip on Substrate Device Interconnection Reliability Analysis
Ying-Chih Lee - Advanced Semiconductor Engineering, Inc.
Wei-Hong Lai - Advanced Semiconductor Engineering, Inc.
Ian Hu - Advanced Semiconductor Engineering, Inc.
Meng-Kai Shih - Advanced Semiconductor Engineering, Inc.
Chin-Li Kao - Advanced Semiconductor Engineering, Inc.
David Tarng - Advanced Semiconductor Engineering, Inc.
Ching-Pin Hung - Advanced Semiconductor Engineering, Inc.

5. 10:25 AM - Embedded Si Fan-Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes
Daquan Yu - Huatian Technology (Kunshan) Electronics Co., Ltd.
Zhenrui Huang - Huatian Technology (Kunshan) Electronics Co., Ltd.
Zhiyi Xiao - Huatian Technology (Kunshan) Electronics Co., Ltd.y
Li Yang - Huatian Technology (Kunshan) Electronics Co., Ltd.
Min Xiang - Huatian Technology (Kunshan) Electronics Co., Ltd.

6. 10:50 AM - Process Development and Material Characteristics of TSV-less Interconnection Technology for FOWLP
Wen-Wei Shen - Industrial Technology Research Institute
Yu-Min Lin - Industrial Technology Research Institute
Hsiang-Hung Chang - Industrial Technology Research Institute
Tzu-Ying Kuo - Industrial Technology Research Institute
Tao-Chih Chang - Industrial Technology Research Institute
Ang-Ying Lin - Industrial Technology Research Institute
Alvin Lee - Brewer Science
Jay Su - Brewer Science
Baron Huang - Brewer Science
Kuan-Neng Chen Chen - NCTU
Huan-Chun Fu - NCTU

7. 11:15 AM - First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency Multi-chip Integration
Tailong Shi - Georgia Institute of Technology
Vanessa Smet - Georgia Institute of Technology
Yoichiro Sato - Asahi Glass Co., Ltd.
Lutz Parthier - Schott
Frank Wei - DISCO Corporation
Cody Lee - DISCO Corporation
Venky Sundaram - Georgia Institute of Technology
Rao Tummala - Georgia Institute of Technology
Chintan Buch - Georgia Institute of Technology